This invention relates to a thin film transistor and, more particularly to the LDD type thin film transistor used in the pixel switching element of liquid crystal display and in its drive circuit, etc. and to their manufacturing method.
Much active in recent years have been the various researches into the liquid crystal display unit using the active matrix type display substrate provided with the thin film transistor (hereafter also referred to as xe2x80x9cTFTxe2x80x9d) for each pixel electrode and the EL display, which give higher picture quality than that of the non-active matrix type display. Further, researched and proposed has been so-called drive circuit incorporating liquid crystal display unit, where the TFT as pixel switching element and drive circuit are formed on the same glass substrate making use of the fact that the electron mobility of polysilicon (hereafter also referred to as xe2x80x9cp-Sixe2x80x9d) TFT is higher by one or two units than that of amorphous silicon (hereafter also referred to as xe2x80x9ca-Sixe2x80x9d) TFT.
However, in this case, there are some technical problems concealed in the nature and performance of the TFT as the semiconductor element itself used in the drive circuit or in its usage for liquid crystal display unit and the like.
Viewed from the standpoint of the nature and performance of the semiconductor element, which is rather the former problems, it should be noted that the p-Si TFT features a larger off current than that of a-Si TFT and MOS type field-effect transistor, and Japanese Provisional Publication 136417-1993 discloses and proposes a thin film transistor where a lightly doped drain (hereafter referred to as xe2x80x9cLDDxe2x80x9d) area is provided in the directly adjoining area of TFT source or drain source area in order to reduce the said off current.
In the simply LDD-structured TFT, however, it is possible to decrease the off current, but the lightly doped drain area, which is relatively high resistance layer, is inserted in series into the channel area when it is turned on where the channel under the gate electrode of TFT does reverse, thereby reducing the on current.
This has led to the proposition of the TFT of various LDD structures with reduced on-current. [SID96, Digest pp.25: Samsung Electronics (hereafter referred to as xe2x80x9cthe first conventional examplexe2x80x9d), Euro Display 1996 pp.555, Asia Display 1995 pp.335: Philips (hereafter referred to as xe2x80x9cthe second conventional examplexe2x80x9d).
FIG. 1 illustrates the construction of the first conventional example. In this figure, the numeral 10 represents a glass substrate. The numeral 150 is the source area (n+ layer) of the semiconductor layer consisting of p-Si, while 160 is the drain area (n+ layer) of the same. The numeral 170 represents the channel area of the same.
In this figure, the subgate electrode 41 is provided as if it covered the gate electrode 4 with the LDD areas (light doped drain area: n-layer) 151 and 161 provided on the semiconductor layer on the source and drain sides beneath the subgate electrode 41. This construction, when it is turned off, makes the semiconductor layers 151 and 161 of the LDD area beneath the subgate electrode 41 a high resistance layer with the carrier being exhausted, and subsequently, this suppresses the off current. However, when it is turned on, the electrons that become carriers will accumulate in the LDD areas 151 and 161, and these areas will become low resistance areas, and therefore no on-current reduction will occurs there.
In reality, these TFTs are formed over several rows and columns in horizontal and vertical directions in response to the standard, etc. of pixels, for instance, at the positions on the substrate that correspond to the drive circuits of each pixel and peripheral portion of the pixel. Through the intermediary of the interlayer dielectric the gate, source and drain electrodes constitute the multilayer interconnection mechanism. However, as these are self-evident matters, their drawings are omitted here, and any individual mentions to the similar effect are limited to the necessary least in any subsequent descriptions and drawings of embodiments.
Next, FIG. 2 depicts the second conventional example. In this figure, the numeral 10 represents a glass substrate. The numerals 150, 160, and 170 respectively represent the source area (n+ layer), drain area (n+ layer), and channel area of the semiconductor layer consisting of p-Si. This figure illustrates so-called TFT of GOLD (Gate-drain Overlapped Lightly-doped Drain, gate-overlapped) structure, and more concretely, the gate electrode 4 is provided as if it hung over the LDD areas (n-layer) 152 and 162 on both sides of the channel area, that is on the source side and drain side. In this construction, as was with the first conventional example, when it is turned off, the lightly doped drain areas 152 and 162 beneath the gate electrode 4 become high resistance layer with the carrier being exhausted, and this therefore allows to suppress the off-current. If, on the other hand, it is turned on, the lightly doped drain areas 152 and 162 will become low resistance areas partly because they are beneath the gate electrode and partly because the electrons that become carrier accumulate there, and therefore, no on-current will reduce there.
However, in any process that actualizes such a TFT structure, the LDD area formed in the polycrystalline silicon semiconductor layer in order to suppress the reduction in on-current has been formed by injecting particular impurities using the ion-doping method. When injecting (or xe2x80x9cdopingxe2x80x9d) particular impurities (different from any xe2x80x9cimpuritiesxe2x80x9d in other technical fields, they are some substances positively injected into the polycrystalline silicon in order for the semiconductor element to display their function; namely, they are not any xe2x80x9ccontaminantsxe2x80x9d), any substance other than the necessary impurities, the hydrogen atoms, for instance, will be doped at the same time. And, in particular, when hydrogen is doped into the channel portion of the polycrystalline silicon just beneath the gate electrode, the hydrogen will come to intervene among the polycrystalline silicon atoms connected with each other, which causes the electrons to be trapped. This will raise the threshold value of voltage of the TFT, thereby remarkably reducing the dependability.
It is therefore indispensable for solving the assignment of the electric characteristics in the p-Si TFT to provide an infinitesimal LDD (lightly doped drain) area adjoining at least to one of TFT""s source area and drain area. However, such difficulties as shown below will arise from forming these lightly doped drain area:
1) High refinement of the liquid crystal display unit requires to miniaturize the pixel transistor to heighten the display density. However, the exposure system that is normally used in the manufacture of liquid crystal display unit is mainly an equifold exposure system, which naturally limits the refinement of the pixel transistor. It is consequently very difficult to form the miniature lightly doped drain area (of the order of 0.1 to 2 or 3 xcexcm) equivalent to or less than the channel width (approximately 1 to several xcexcm) of the pixel transistor.
2) Since the superposition of the subgate electrode over the lightly doped drain area is made by mask overlaying, these superpositions cannot be made self-consistently (inevitably well superposed at a high accuracy when viewed from the injection direction of the impurities). The deviation in the mask overlaying causes the dimensions of the lightly doped drain area to vary, which in turn requires some margin for the mask overlaying because of the process control for manufacturing in a limited short period of time, and this restricts the refinement of the pixel TFT. In consequence, the occupancy area of the pixel TFT will increase as much as the margin is assured.
3) As the occupancy area of the pixel TFT grows larger, the parasitic capacitance between the source and drain areas increases accordingly. As a result, the working waveform is caused to delay, thereby reducing the display characteristics of the liquid crystal display unit.
4) When forming the subgate electrode, it requires the process of forming the metallic film, which is an electrode, as well as the photolithographic process and etching process besides the gate electrode, and further it requires the photomask to perform the photolithography. This GOLD structure therefore requires not merely two times of ion injection but such a complicated manufacturing process as oblique rotation ion injection. Accordingly, the TFT manufacturing process becomes to be divergent, and the prolongation of the process, the increased manufacturing cost, and the reduced yield will make the liquid crystal display markedly expensive.
Next, when we are going to describe the assignment viewed rather from the standpoint of usage to the liquid crystal display unit, although there are some phases that may more or less overlap with the previous descriptions on the assignment, they are as explained as the following.
In the TFT used in any liquid crystal display unit, the higher resistance of gate line will first elicit the problem of the electric resistance of the gate line in such larger picture as 15 inches and 20 inches.
That is, we cannot neglect the delay of gate signal any more, and the delay in response of the pixel becomes remarkable. Further, there will also arise such inconveniences as flicker and display unevenness of the picture.
Second, the TFT characteristics becomes problematic.
As for the TFT characteristics, important are the enhanced mobility, the improved on-current, and the reduced and stabilized threshold voltage. And, the control of the interface is the most important to enhance these characteristics. In particular, the interface between the semiconductor layer and the gate insulator will exert not a little influence. Consequently, this interface, if improved, will assuredly contribute to the enhancement of the characteristics.
One of the means to improve the interface is heat treatment. The heat treatment will decrease the interfacial defect, remove the electric charge accumulated in the respective layers, thereby enhancing the interface. The temperature of this heat treatment is preferably 800 to 900xc2x0 C. where the silicon constituting the semiconductor layer recrystalizes.
The improvement is however restricted because the glass substrate has been adopted in the display unit because of economical reason. As such, the maximal allowable temperature is limited to the approximate 600xc2x0 C. due to the heat resistance of glass as defined from the thermal shrinkage.
To a bad circumstance, tentative use of aluminum or aluminum alloy-based low resistance metal as a means to decrease the resistance of gate electrode for solving the first problematic point aforementioned might cause such an inconvenience as hillock, disconnection, and short-circuit even at that counterproductive 600xc2x0 C. of temperature. If, on the contrary, such a high melting point metal as W, Mo and Ta is used, it will still worsen the above-mentioned inconvenience, because such high melting point metals feature high resistance.
Third, there arises a leak current as a problematic point.
That is, in the thin film transistor, the data retentivity of the pixel lessens if the leak current grows in the off area. It is therefore very important to reduce the off leak current in order to obtain a highly refined excellent pixel. In the conventional thin film transistor, there arises the off leak current by the electric field strength in the vicinity of the drain area. Therefore, increasing the gate voltage toward the off side will increase the field strength, and subsequently increase the off leak current as well. As the countermeasure, the LDD (lightly doped drain) and offset structures have been adopted conventionally. It is nevertheless difficult to form a precisely appropriate LDD area from the dimensional viewpoint. Fourth, on a sheet of the substrate are provided with a pixel portion and a part of its drive circuit, whose roles are different from each other, and the TFT characteristics required for these parts also differ. Although, in this case, the geometrical form of element and the dimensions of channel, drain and source areas may be coped with by the masking design in the photolithography, this countermeasure is hardly applied to any refined LDD portion.
Fifth; if on a sheet of substrate are provided with the pixels, TFT for pixel, TFT for drive circuit, and reflection board, whose roles are different from each other, the process will inevitably compelled to increase in the number. However, unless these formations are not made common to the furthest possible degree, manufacturing cost of these may necessarily be increased.
It has therefore long been craved for a commercialization of a semiconductor element using a gate electrode featuring small electric resistance and excellent heat resistance, which in its turn may lead to excellent TFT characteristics and little leak current, resulting in easier manufacture and in restricting any cost increase despite the LDD structure.
It has further been longed for the thin film transistor with little parasitic capacitance formed with a high accuracy from infinitesimal LDD structure, and the development of their extremely simple and easy manufacturing.
Further, such LDD type TFT that may satisfy such requirements had been expected to be developed irrespectively of the top gate type or bottom gate type.
Also desired had been the development of a sheet of the substrate, on each part of which is formed the LDD-type TFT featuring the characteristics required for the said respective portions, and that of a liquid crystal display unit with a large screen featuring quick responsiveness of the pixel without any flicker.
In the p-Si TFT, not to say the LDD type, the hydrogen used for dilution at the time of injecting (doping) impurities intrudes into the channel area beneath the gate electrode to damage the silicon crystals, which largely impedes the characteristics of p-Si TFT. As such, solving this problematic point was also long craved for.
Also longed for were the formation of the LDD-type TFT featuring different characteristics at respective parts of a sheet of the substrate, the development of a technology that can reduce as much as possible the forming processes of the pixels on the TFT and substrate, and other elements such as the reflection board, and finally the development of a LDD-type TFT that can meet these requirements.
This invention, which is intended to resolve the foregoing assignments, cogitates the material and construction of the gate electrode in the aspects of its electric resistance and injection (doping) of impurities, among others. Further, it exerts inventor""s ingenuity in the manufacture and structure of the source and drain electrodes. Contrivance has been also made in the manufacture of panel.
Hereunder, we are going to describe more in detail the conception of this invention.
[First Group of Inventions]
In this group of inventions, a silicide is used to form an infinitesimal portion that is weaker in masking capacity and shorter in channel direction than the central portion when impurities are injected at the ends of the source electrode and drain electrode sides in order to improve the gate electrode and form the LDD area.
According to one of the inventions belonging to this group, in the semiconductor element having, on the substrate, a semiconductor layer provided with a source area, drain area, and a gate area, the gate insulator, as well as the source electrode, drain electrode, and the gate electrode formed on the gate insulator, [also including other portions such as the interlayer dielectric required to display the function as a transistor (element)], the gate electrode is composed of the two layers, i.e. the upper and the lower, which are consisted of a silicide film and a metallic film, and further on the upper layer is formed so that it may completely cover the lower layers when viewed from the flying direction of the ions of the impurities to be injected (doped), and the semiconductor layer has an LDD area that is formed by injecting the impurity ions using the gate electrode of this multilayer structure as an injection mask.
The above structure allows for such a function as follows. One of the layers of the gate electrode of the semiconductor element is a silicide film (it may somewhat contain other substances such as material silicon due to some reasons such as nonreactive) and the other layer consists of the two (upper and lower) layers that are metal films. A further upper layer hangs over the lower layer (on the gate insulator side) as if the former completely covers the latter when viewed from the flying direction of impurities (upper face of the substrate, in principle). In most cases, this layer has been jutted out, by 1 to 4 xcexcm suited to form the LDD structure (depending on such conditions as the size of element) toward at least one of the drain electrode side and source electrode side.
The semiconductor layer has an LDD area where the quantity of injected impurities is made naturally smaller than in the channel area on at least one side of the drain electrode and source electrode side by injecting the ions of impurities from above, adopting the gate electrode as the injection mask, in the construction of which said upper layer juts out, or the overall cross sectional part is in the form of a trapezoid extending downward.
Resulting from the above configuration, the source area, drain area, and narrower LDD area have come to be naturally formed in the area to be decided by the position occupied by the silicide film and metallic film in the semiconductor layer and the injection direction of the impurity ions.
If describing by way of precaution, there may arise a case where the impurities are diffused with the delimitation rendered more or less ambiguous due to the subsequent heat treatment. Further, there is another case where the injection direction of the impurity ions become slightly oblique upward. However, these cases are also included in the framework of this invention.
From the above, it results that the LDD area is molded on the downstream side in the ion flying direction in the portion where the second layer of said upper side juts out. Note in this case that if the jutting out is deviated only toward one direction, the stray capacitance will become smaller.
In some other inventions, the two layers (upper and lower) consisting of the silicide film and metallic film are replaced by the two layers (upper and lower) of the silicide film and silicide film (including the existence of more or less nonreactive layer) by, for example, a chemical reaction between the silicon film and metal film, regardless of whether the thickness is the same or not.
The aforementioned configuration allows for a function similar to that of the prior invention for the formation of the LDD area. (Adding few more words by way of precaution, different from kind of like perfect crystalline silicon with far larger grain size, the polycrystalline silicon formed by laser annealing may be formed into the silicide within a shorter period of time at the temperature even the glass substrate may withstand.)
In some other inventions, the gate electrode is the gate electrode combining a multistage LDD forming mask consisting of the multiple layers having such silicon film as amorphous, which is more likely to react with at least the silicide thin film and metal thin film, and the central portion is the thickest as the mask used when impurities are injected, the both ends being thinnest, and the intermediate portion having an intermediate thickness or becoming gradually thicker toward the central portion from both ends.
From the above configuration, it results that this invention has a multistage LDD area.
In other inventions, the gate electrode is a gate electrode containing an intermediate aluminum layer having a layer consisting of such high melting point metals (including alloys) as molybdenum, tungsten, tantalum, niobium, TZM, and TZC, a layer consisting of the silicide film, and a layer consisting of the aluminum film surrounded by high melting point metallic film layer and silicide film layer. And, the semiconductor layer is an LDD semiconductor element that has the single or multistage LDD area formed by injecting the impurity ions from above using the intermediate aluminum layer gate electrode as an injection mask.
The aforementioned configuration allows for the following functions.
The gate electrode being a gate electrode containing an intermediate aluminum layer, it in fact hardly reacts with aluminum at the heat treatment temperature of substrate, and it has therefore come to have a layer consisting of a high melting point metal film not susceptible to any deformation, a layer consisting of a silicide film of similar nature, and an aluminum film with the low electric resistance surrounded by a high melting point metal film layer and silicide film layer, and protected by these layers when the substrate is thermally treated. Therefore its electric resistance is low and heat resistance is excellent.
In other inventions, the silicide layer is the silicide layer from particular material to be selected from the group of titanium silicide, cobalt silicide, nickel silicide, zirconium silicide, molybdenum silicide, palladium silicide, and platinum silicide.
From the above configuration, the silicide layer comes to be selected from a group of the low electric resistance titanium silicides (TiSi2, TiSi, Ti5Si3), cobalt silicide (CoSi2, CO2Si, CoSi, CoSi3), nickel silicides (Ni2Si, NiSi, NiSi2), zirconium silicides (ZrSi2, ZrSi, Zr2Si), molybdenum silicides (MoSi2, Mo3Si, Mo5Si3), palladium silicides (Pd2Si, PdSi), and platinum silicides (Pt2Si, PtSi).
The molecular formulas of respective metal silicides are enumerated illustratively.
In other inventions, at least one of the metal films is a metallic film where the constituting metal element is the same with the metal element that constitutes the silicide.
The aforementioned configuration makes it possible that a metal element same as the first layer is used as the material so that, for example, the metal element is palladium film if the silicide of the first layer is palladium silicide. This makes it easier to form the silicide layer and arrange for the material.
In other inventions, the manufacturing method of the LDD type TFT is as above.
[Second Group of Inventions]
Since in this group of inventions the gate electrode serves also as the mask when impurities are injected to manufacture the LDD-type TFT, when forming the gate electrode the thickness of which changes in multiple stages, the plating based on the gate electrode constituting the material layer readily formed on the gate insulator, oxidation, anodic oxidation, and other similar processing, as well as the photolithography, etching, etc. are used.
In one of the inventions belonging to this second group, as with the first invention in the first group of the inventions, as the gate electrode is made the LDD structure being used as the mask as well when impurities are injected, the lower electrode is employed to form an upper electrode above the former, and at this time, as for at least one side of either the source electrode side or the drain electrode side, either the upper electrode or the lower electrode juts out somewhat from the other, and the masking capacity of the said jutted-out portion is made imperfect.
The foregoing configuration allows for the following function.
In the semiconductor layer, a channel area is formed just beneath the central portion of the gate electrode, an LDD area just beneath the jutted-out portion of at least one side thereof, and further respective source and drain areas in any areas other than the above.
In other inventions, the upper gate electrode is formed by plating a metal film composed of the material which is in principle small in density on the readily formed lower gate electrode composed of a material which is in principle large in density. (Needless to say, the density is not always as such, depending on the thickness of the lower gate electrode film, shielding, masking capacity, plating thickness, and materials.)
The above-mentioned configuration allows for the following function.
Because the upper gate electrode is plated, it is very thin featuring excellent accuracy in thickness, and it is formed on the lower electrode on a very exact position.
In other inventions, the plating is either electrolytic or electroless plating.
This is convenient from the viewpoint of broader selection of the materials, waste disposal, and so forth.
When the upper gate electrode is formed by plating, unless otherwise processed beforehand, the jut-out portions over the lower electrode side are formed both on both the source electrode side and drain electrode side, and it is needless to say that plating is made on the upper face of the lower electrode as well.
In other inventions, the material of the upper gate electrode is anodized to form the mask for shaping the LDD.
In other inventions, the lower gate electrode such as Mo and Fe is made to react with predetermined object, for instance, with such gas as oxygen, and the mask for forming the upper LDD is shaped by using the chemical reactions such as forming the oxides on its upper and lateral faces, etc.
The aforesaid configuration allows for the following function.
In this case as well, the upper gate electrode can be formed with exact positioning and thickness by controlling the temperature, fluid pressure, etc. when the reaction is started.
In the case as above, the electric resistance may become high enough depending on the combination of the lower gate electrode material with reactive object, the upper gate electrode does not in fact function as its role, and instead may only serve s a mask. The principle in such a case should be that the upper gate electrode as a result of reaction after the injection of impurities is removed by etching, or may serve as an insulator.
In other inventions, first the lower gate electrode with solid masking function is formed, and then the impurities are gently injected, and afterward the upper gate electrode with a solid masking function that is jutted out at least either on the source electrode or on the drain electrode side is formed on the upper part of the lower gate electrode by plating, and further the impurities shall be squarely injected beneath them.
The configuration as above allows for the following function.
The impurity injection is thus required twice. However, the TFT having the LDD area in the jutted out lower portion of the upper gate electrode can be manufactured.
In other inventions, the protrusion, namely the jutted-out portion on the lateral end of the lower gate electrode of the upper gate electrode can be formed by using at least the photolithography and etching.
The aforesaid configuration allows for the following function.
A gate electrode serving also as the mask is formed to form the LDD structure where there is less deviation of the lower gate electrode from the upper gate electrode.
In some cases, such other means as anodization may be adopted along with these ones. Further it is probable that a resist may constitute a part of the mask.
In other inventions, the projection of the mask cum gate electrode, of which construction is that the upper and lower two stages and the upper stage juts out against the lower stage, shall be removed after the injection of impurities.
The foregoing configuration allows for the following function.
It becomes possible to form the LDD-TFT, the characteristics of which are different from each other, on a sheet of the substrate. The substrate becomes most suited to varied usages by forming this LDD type TFT only in a part of the area of same substrate corresponding to the role played by the element, or to the required performance. In addition to the above, both the first and second groups of the inventions as well as the several other inventions use, as the materials for the upper and lower gate electrodes, such metals (including silicide) with great hydrogen adsorption, particularly Ti, or other alloys having Ti as the primary component, or metals whose density is 8 or higher, more preferably 10 or higher, yet more preferably 13 or higher, more concretely such alloy as Ta and W of higher density, or any other material composed of these alloys or mixtures (W and Ti, for example) into which the hydrogen hardly penetrates when impurities are injected, and the material with low electric resistance.
[Third Group of Inventions]
In this group of the inventions, in addition to the first and second groups of the inventions, the gate insulator in the areas other than that just beneath the mask cum gate electrode is once removed before injecting the impurities to re-form the gate insulator in the said area after the impurity injection.
The above-mentioned configuration allows for the following function.
Because there exists no gate insulator, the acceleration voltage at the time of injecting the impurities may be as much lower proportionately, and consequently the damage of polycrystalline semiconductor due to the high-speed injection of the hydrogen used to dilute the impurities will become as much less accordingly irrespective of the channel, source, drain and LDD areas.
It goes without saying that certain heat treatment is performed as occasion arises in order to limit, and recover from, the damages of the polycrystalline semiconductor accompanying the removal of the gate insulator.
[Fourth group of Inventions]
In this group of the inventions, in particular, in addition to the third of the inventions, Ti or Zr film with excellent hydrogen absorption capacity is formed beforehand on the upper surface of the polycrystalline semiconductor after once removing the gate insulator in order to prevent, as far as possible, the hydrogen for diluting the impurities at the time of their injection from penetrating into the polycrystalline semiconductor.
The foregoing configuration allows for the following function.
Ti, etc. and further the hydrogen absorbed into Ti, etc. injected together with the impurities are physicochemically adsorbed, and reduced in rate, thus preventing the hydrogen from penetrating into the polycrystalline semiconductor at a high speed. Needless to say, these metals, especially Ti with smaller density does not so much hinder the injection of impurities.
Therefore, the performance of the LDD-TFT will further be improved.
In other inventions, Ti, etc., such as the hydrogen stopper, at the time of impurity injection shall be left alone in the area where the source and drain electrodes are formed, and the subsequent heat treatment makes them react with the polycrystalline silicon to form the silicide film.
The configuration such as mentioned above will allow for the following function.
The electric contact with the source electrode and drain electrode and with the polycrystalline silicon will be by leaps and bounds improved through the intermediary of the silicide layer.
Further, when contact holes are opened to form the source electrode and drain electrode, the layer of the silicide film or nonreactive Ti, etc. remaining on the upper face of the silicide film will serve as an etching stopper.
[Fifth Group of Inventions]
This group of the inventions is almost the same with the foregoing first to fourth groups of the inventions in every respect, except that the former is a bottom gate type, and the latter a top gate type.
Provided always that this group of the inventions has its own configuration where resin is exposed by irradiation of visible light or X-ray from the substrate side in order to form the mask at the position exactly corresponding to the gate electrode.
[Sixth Group of Inventions]
This group of the inventions is different from the first to fourth groups of inventions in that the former is non-LDD type while the latter LDD type. The purpose of this invention is to get a gate electrode with a low resistance preventing the hydrogen from penetrating into the lower portion of the channel area.
In one of the inventions, therefore, the gate electrode is divided into the two layers, one of which is formed from the material of a lower electric resistance, and other layer from the high-density metal or hydrogen adsorbing metal, among others.
In another invention, the gate insulator is once removed when the impurities are injected.
In yet another invention, the Ti film is formed after once removing the gate insulator in order to prevent the hydrogen infiltration. Note that this film shall in principle be removed once the impurities are injected.
[Seventh Group of Inventions]
This group of the inventions relates to the substrate using the LDD-type TFT, while all the above-mentioned invention groups relate more particularly to the LDD-type TFT itself.
Formed on each part of a sheet of the substrate in one invention is the LDD-type TFT, whose characteristics correspond to the roles of the said respective parts.
In other inventions, formed on the respective parts of a sheet of the substrate are varied parts, the films and layers responding to the roles of the said parts. And, their formation and that of the LDD type TFT in the aforesaid groups of the inventions have been rendered interchangeable as far as possible.